1. Field of Invention
The present invention pertains to the field of non-volatile memories. More particularly, this invention relates to a non-volatile memory array that includes self-aligned dual function bit lines and asymmetrical source and drain junctions.
2. Description of the Related Art
Prior non-volatile memories typically include an array of memory cells which are accessible via a matrix of control lines. Such control lines typically include dedicated bit lines that couple to the drain regions of the memory cells. In addition, such control lines usually include word lines that couple to the control gates of the memory cells and dedicated V.sub.SS lines that couple to the source regions of the memory cells.
Such dedicated bit lines are typically formed from a metal such as aluminum. Such word lines are commonly formed of a polysilicon material or polycide material that includes a refractory metal. Such prior memory arrays typically include drain contact areas that provide electrical coupling between the drain regions of the memory cells and the dedicated bit lines.
Such drain contact areas are usually defined by the photo lithographic printing equipment employed in the particular memory device manufacturing process. Typically, such printing equipment is characterized by a minimum feature size for forming areas on the memory array including the drain contact areas. As a consequence, each drain contact area consumes a fixed minimum area of integrated circuit die space according to the minimum feature size inherent with the particular printing equipment.
Unfortunately, the integrated circuit die space consumed by such drain contact features limits the density of a memory array for a given area of integrated circuit die space. Such density limitations commonly require that high capacity memory arrays be implemented on larger silicon substrates. Such larger silicon substrates usually increases the overall cost of such memory devices.
One prior method for eliminating such drain contact features in a non-volatile memory array is to employ an array architecture that may be referred to as a virtual ground architecture. Such a virtual ground array includes dual-function control lines that function as both bit lines and V.sub.SS lines. Such a virtual ground array usually obviates the need for forming drain contact features for dedicated bit lines.
The dual function control lines in prior virtual ground memory arrays are typically formed by masking, dopant implant, and thermal diffusion process steps. Such a process that employs masking and thermal diffusion process steps usually causes migration of the implanted dopant into areas outside of the control line areas defined by the mask. Such dopant migration typically requires increased spacing of control lines in order to provide electrical isolation of the control lines from other areas of the memory array. Unfortunately, such increased spacing of control lines usually reduces the density of memory cells formed by such a process.